They’ve been moved one stage to the left. Generate the next bit are the same as the ones shown in Fig 2, save only that If you compare Fig 3 with Fig 2, you can see how the taps to You can see this how this would affect our The first part will be due to the bits in sreg. To get there, let’s split this new equation into two parts. We’ll have to get rid of the reference to sreg, though, before this Our equation for the next bit, and apply it to bits to get bit Now let’s see what it will take to calculate bit MSB+2. MSB:0 bits have no required relationship between them–save that they cannot You may also remember, from the discussion of an When we presented this equation, we had bits MSB:0 definedĪnd we just needed to calculate the next bit, MSB+1, sreg = ^ ( sreg & TAPS ) Let’s begin our development by imagining an infinite stream of (constant)īits in our shift register, sreg. With a feedback equation defined by TAPS=5'b00101. The question, though, is how shall we do this? Fig 2: Example LFSRįor discussion and as an example along the way. That produces WS bits at a time–rather than just one. That our resulting implementation actually works. We’ll also do one more: let’s formally prove at the end of our development, Getting these extra bits, and then discuss the code that implements this. We’ll start with describing how we’ll go about
So the only thing that needs to change today is the number of outputsīits we need to generate. To drive an output serializer at high speed.Īnd see if we can modify it to produce more than one output per clock Generated one bit per clock, and I will need several bits per clock in order Indeed, if all goes well I should be able to apply Shannon’s Capacity Representing my channel, and examine the waveform at the other end to getĪn estimate of the channel throughput and I’ll then receive the bits at the other end of a My intention was to use a setup like Fig 1 to the right. However, neither of these developments have solved the problem I had
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